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Chapter 7 Counters
NI 6232/6233 User Manual 7-34 ni.com
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 7-29 shows an example of a low-to-high
transition on an input that has its filter set to 125 ns (N = 5).
Figure 7-29. Filter Example
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.55 ms setting, the
jitter is up to 10.025 µs.
When a PFI input is routed directly to RTSI, or a RTSI input is routed
directly to PFI, the M Series device does not use the filtered version of the
input signal.
Refer to the KnowledgeBase document, Digital Filtering with M Series
and CompactDAQ, for more information about digital filters and counters.
To access this KnowledgeBase, go to
ni.com/info and enter the info
code
rddfms.
Prescaling
Prescaling allows the counter to count a signal that is faster than the
maximum timebase of the counter. M Series devices offer 8X and 2X
Table 7-5. Filters
Filter Setting
N (Filter
Clocks Needed
to Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns 5 125 ns 100 ns
6.425 µs 257 6.425 µs 6.400 µs
2.55 ms ~101,800 2.55 ms 2.54 ms
Disabled — — —
1231 4 12345
RTSI, PFI, or
PXI_STAR Terminal
Filter Clock
(40 MHz)
Filtered Input
Filtered input goes high
when terminal is sampled
high on five consecutive
filter clocks.
- DAQ M Series 1
- Important Information 3
- Compliance 5
- Chapter 3 7
- Chapter 4 7
- Chapter 5 8
- Chapter 6 9
- Chapter 7 9
- Contents 10
- About This Manual 13
- Related Documentation 14
- NI-DAQmx Base 15
- LabWindows 16
- Measurement Studio 16
- Training Courses 17
- Technical Support on the Web 17
- Getting Started 18
- Device Specifications 19
- Device Accessories and Cables 19
- DAQ System Overview 20
- DAQ-STC2 21
- Sensors and Transducers 22
- Cables and Accessories 23
- Chapter 2 DAQ System Overview 24
- Connector Information 25
- Analog Input 28
- Analog Input Range 29
- (10 V – (–10 V)) 30
- = 305 mV 30
- Figure 4-2. PGIA 31
- Software 32
- Use Low Impedance Sources 33
- Chapter 4 Analog Input 34
- Example 1 36
- Example 2 36
- Software-Timed Acquisitions 36
- Hardware-Timed Acquisitions 37
- Buffered 37
- Analog Input Triggering 38
- Types of Signal Sources 39
- Floating Signal Sources 40
- Differential Input Biasing 42
- Signal Sources 44
- Field Wiring Considerations 45
- Analog Input Timing Signals 46
- Sample Counter 48
- AI Sample Clock Signal 49
- Using an Internal Source 50
- Using an External Source 50
- Terminal 50
- Other Timing Requirements 50
- AI Convert Clock Signal 52
- AI Hold Complete Event Signal 55
- AI Start Trigger Signal 55
- Using a Digital Source 55
- AI Reference Trigger Signal 56
- AI Pause Trigger Signal 57
- Software-Timed Generations 60
- Hardware-Timed Generations 61
- Non-Buffered 61
- Analog Output Triggering 62
- Analog Output Timing Signals 63
- AO Start Trigger Signal 64
- AO Pause Trigger Signal 65
- AO Sample Clock Signal 66
- Chapter 5 Analog Output 68
- Digital Input and Output 70
- Logic Conventions 72
- Terminals section 75
- Counter Input Applications 76
- Pulse-Width Measurement 79
- Period Measurement 80
- Single Period Measurement 81
- Buffered Period Measurement 81
- Semi-Period Measurement 82
- Frequency Measurement 83
- Counter (Averaged) 84
- Using Two Counters 86
- Figure 7-14. Method 3 87
- Position Measurement 89
- X2 Encoding 90
- X4 Encoding 90
- Channel Z Behavior 90
- 890 21743 91
- Counter Output Applications 94
- Pulse Train Generation 96
- Frequency Generation 97
- Using the Frequency Generator 97
- Frequency Division 98
- Pulse Generation for ETS 98
- Counter Timing Signals 99
- Counter n Source Signal 100
- Counter n Gate Signal 101
- Counter n Aux Signal 101
- Counter n Up_Down Signal 102
- Counter n HW Arm Signal 103
- Default Counter Terminals 104
- Counter Triggering 105
- Other Counter Features 106
- Prescaling 107
- Duplicate Count Prevention 108
- Duplicate Count Example 109
- Chapter 7 Counters 110
- Synchronization Modes 111
- 80 MHz Source Mode 112
- Other Internal Source Mode 113
- External Source Mode 113
- Chapter 8 PFI 115
- Connecting PFI Input Signals 116
- PFI Filters 117
- I/O Protection 118
- Programmable Power-Up States 119
- Table 9-1. Ground Symbols 122
- Digital Isolation 123
- Digital Routing and Clock 124
- Generation 124
- 80 MHz Timebase 125
- 20 MHz Timebase 125
- 100 kHz Timebase 125
- External Reference Clock 125
- 10 MHz Reference Clock 126
- RTSI Connector Pinout 127
- Using RTSI as Outputs 128
- RTSI Filters 129
- Figure 10-3. Filter Example 130
- Table 10-2. Filters 130
- PXI Clock and Trigger Signals 131
- PXI_STAR Filters 132
- Figure 10-4. Filter Example 133
- Bus Interface 134
- PXI Considerations 135
- Data Transfer Methods 136
- Interrupt Request (IRQ) 137
- Programmed I/O 137
- Triggering 138
- • Analog output generation 139
- • Counter behavior 139
- Device-Specific Information 140
- Figure A-1. NI 6232 Pinout 141
- NI 6232 Specifications 142
- Screw Terminal 142
- NI 6233 Pinout 143
- Figure A-2. NI 6233 Pinout 144
- NI 6233 Specifications 145
- Troubleshooting 147
- Channel 0 148
- Channel 1 148
- Convert Period 148
- Sample Period 148
- Analog Output 149
- Counters 149
- Technical Support and 150
- Professional Services 150
- Glossary 152
- Numerics 171
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